The present invention relates generally to data processing systems, and more particularly to processing in different contexts using a processor.
Many current computer systems use virtual memory systems to manage and allocate memory to various processes running within the system, which allow each process running on the system to operate as if it has control of the full range of addresses provided by the system. The operating system (OS) maps the virtual address space for each process to the actual physical address space for the system. Mapping from a physical address to a virtual address is typically maintained through the use of page tables.
Processor performance is improved via a multiple-stage pipeline architecture, in which various pipeline resources, such as caches, buffers, arrays, and the like may be used to more efficiently execute instructions. One such pipeline resource that improves use of virtual memory systems is a translation lookaside buffer (TLB). A TLB is a relatively small section of memory in a processor pipeline which caches part of the system's virtual address to physical address translations. Specifically, a few elements of the translation set are stored in the TLB which the processor can access extremely quickly. Various TLBs may exist in a system. For example, separate TLBs may exist for instructions and data (respectively, an instruction TLB (iTLB) and a data TLB (dTLB)). More so, in certain systems a second level dTLB (STLB) may be present.
If a translation for a particular virtual address is not present in the TLB, a “translation miss” occurs and the address translation is resolved using more general mechanisms. Processing in this manner continues until a context switch occurs. A context switch may occur when a multitasking OS stops running one process (e.g., an application) and begins running another. When a context switch occurs, page tables including a page directory and a page table for the new process are loaded, and the TLB and other pipeline resources must be flushed. By flushed, it is meant that the resources' contents are cleared.
Certain systems may implement a virtual machine (VM) environment in which a virtual machine monitor (VMM) presents to other software the abstraction of one or more virtual machines. Each VM may function as a self-contained platform, running its own “guest operating system” (i.e., an OS hosted by the VMM) and other software, collectively referred to as guest software (or simply a “guest”). The guest software expects to operate as if it were running on a dedicated computer rather than a virtual machine. Accordingly, the guest software expects to control various events and have access to hardware resources, such as processor-resident resources, resources that reside in memory and resources that reside on the underlying hardware platform.
In a virtual machine environment, the VMM generally has ultimate control over these events and hardware resources to provide proper operation of guest software and for protection from and between guest software running on different virtual machines. To achieve this, the VMM typically receives control (i.e., effects a context switch) when guest software accesses a protected resource or when other events (such as interrupts or exceptions) occur.
Context switches in a VM or other environment cause considerable overhead in modern microprocessors. This overhead is exacerbated by large second level TLBs that must be flushed and reloaded on every context switch. Thus this overhead can adversely impact performance, especially in systems with many active contexts. A need thus exists to more efficiently maintain pipeline resources on context switches.